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One-bit digital-to-analog converters (DACs) are a practical and promising solution for reducing cost and power consumption in massive multiple-input multiple-output (MIMO) systems. However, the one-bit precoding problem is NP-hard and even more challenging in frequency-selective fading channels compared to the flat-fading scenario. While block-wise processing (BWP) can effectively address the inter-symbol-interference (ISI) in frequency-selective fading channels, its computational complexity and processing delay can be too high for practical implementation. An alternative solution to alleviate the processing complexity and delay issues is symbol-wise processing (SWP) which sequentially designs the transmit signals. However, existing SWP work leaves unwanted interference for later signal designs. In this paper, we propose an SWP approach which can efficiently address the ISI even at the symbol rate. The idea is to design the transmit signal to not only be beneficial for its time slot, but also to provide constructive interference for subsequent symbols. We develop two active ISI processing methods that significantly outperform a conventional approach, one of which that even outperforms the BWP approach at low SNR.